I am looking for information on the history and development of ISAs as a technology. Including:
- Why were they invented? (IBM wanted to sell their customers hardware upgrades without requiring that they rewrite their code?)
- What was early sentiment towards them like? (From users, from compiler-writers, from other CPU designers...)
- What was their adoption story like? How long did it take before they were basically totally ubiquitous, as today?
- What were the _social_ factors that caused GPUs to expose primarily higher-level interfaces, leaving the lower-level ones unstable and mostly unused, unlike CPUs?
I am looking for information on the history and development of ISAs as a >technology. Including:
- Why were they invented? (IBM wanted to sell their customers hardware >upgrades without requiring that they rewrite their code?)
- What was early sentiment towards them like? (From users, from >compiler-writers, from other CPU designers...)
- What was their adoption story like? How long did it take before they were >basically totally ubiquitous, as today?
- What were the _social_ factors that caused GPUs to expose primarily >higher-level interfaces, leaving the lower-level ones unstable and mostly >unused, unlike CPUs?
Any pointers?
As a start, in early machines (late 50's), the term 'instruction'
hadn't yet become common - they used the term 'order' instead. Even
into the 90's, the processor instruction verification suite at
Burroughs was called "all-orders".
This always was a terrible model. For a long time it hindered development
of open source drivers for GPUs, leaving only (ugh!) Windows having drivers that supported all the features. I don’t really follow the situation that closely, my impression is that this has gotten a lot better but is still
not perfect. GPU designers really need to open up their specs.
I am looking for information on the history and development of ISAs as a >technology. Including:
- Why were they invented? (IBM wanted to sell their customers hardware >upgrades without requiring that they rewrite their code?)
It appears that Elijah Stone <elronnd@elronnd.net> said:
I am looking for information on the history and development of ISAs as a >technology. Including:
- Why were they invented? (IBM wanted to sell their customers hardware >upgrades without requiring that they rewrite their code?)
As others have noted, it sounds like you mean computer architecture, not ISA.
In the early 1950s it was a miracle when computers worked at all, and programs had to be written to work around hardware bugs and
idiosyncracies. I heard of a machine where you couldn't have too many
"1" bits in any word because the voltage in the Williams tubes used
for main memory wasn't strong enough.
I'd say the IBM 704 in 1954 was the first computer that really worked.
It had core memory so you didn't have to worry about bit patterns and
a conservative tube design that would run programs reliably for hours
at a time which in that era was a big deal. It also had hardware
floating point and high quality peripheral devices adapted from IBMs
card equipment. People wrote a lot of software for it, including
the first Fortran compiler and a lot of Fortran programs. The next
machine, the 709, had a superset of the 704's ISA so it could run the
same software, the 7090 was a faster transistor version of the 709, and
so forth. They also had some decimal business machines starting with
the 702 and 705. One time they came out with a new business machine
which was faster and better but incompatible with the previous ones,
the customers said Nope, and they quickly came up with a compatible
upgrade. They also had a small business line, the 1400, and small
scientific 1620.
By 1960 it was well established that software was a big investment,
and it was important that new compters run existing software, and it
was increasingly expensive for computer makers to maintain multiple
product lines so everyone could upgrade. IBM then bet the company on
System 360, which was the first design where they started with the archictecture and then built multiple implementaions that ran faster
or slower and could have larger or smaller memory. This is the classic article:
https://www.researchgate.net/publication/220498837_Architecture_of_the_IBM_System360
The 360 wasn't compatible with any of the older machines but they made
a bet, which turned out to be a good one, that they could get people
to convert once in return for the promise that the 360 architecture
would last forever so they wouldn't have to convert again even as they
moved to larger or smaller models. (This was true, modern zSeries
mainframes still run S/360 code.) They also hedged their bets a
little; all but the fastest 360s were microprogrammed, and they
offered microcode compatibility packages. If, for example, you had a
360/65, you could boot it up in 7094 mode and it would run 70x code
faster than any real 70x machine until you finished rewriting or
recompiling your programs into 360 code.
The plan was also that there would be one operating system and one set
of applications but that failed because the OS/360 operating system
turned out to be way too big to run on the smaller machines. So they
quickly came up with cut down systems DOS and TOS (Disk and Tape) and
very simple BOS (Basic). That turned out to be OK, too. OS and DOS are
still around in greatly evolved form, and still run OS and DOS code
from the 1960s.
The 360 was such a great success that we now often forget how
revolutionary it was. It was not only the first architecture intended
from the outset to have multiple implmementations, but it was also the
first one with 8 bit bytes and the kind of byte addressing that is now
used everywhere, and the first popular machine with a large regular
set of registers.
--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly
I'm sure the Wheelers will be along shortly to tell of their involvement.
- a Big Thing that you omitted about the 360 was the invention?/use of VM.
The 360 was such a great success that we now often forget how
revolutionary it was. It was not only the first architecture intended
from the outset to have multiple implmementations, but it was also the
first one with 8 bit bytes and the kind of byte addressing that is now
used everywhere, and the first popular machine with a large regular
set of registers.
I'm sure the Wheelers will be along shortly to tell of their involvement.
- a Big Thing that you omitted about the 360 was the invention?/use of VM.
By the way, on Lynn's web site it says he's been posting like crazy on Facebook in the past month, but I haven't checked.
On Sat, 2 Sep 2023 09:53:51 +0100
"Kerr-Mudd, John" <admin@127.0.0.1> wrote:
Oh dear, Lynn Wheeler last posted back in April, without Anne.
The 360 was such a great success that we now often forget how
revolutionary it was. It was not only the first architecture intended
from the outset to have multiple implmementations, but it was also the
first one with 8 bit bytes and the kind of byte addressing that is now
used everywhere, and the first popular machine with a large regular
set of registers.
John Levine <johnl@taugh.com> schrieb:
The 360 was such a great success that we now often forget how
revolutionary it was. It was not only the first architecture intended
from the outset to have multiple implmementations, but it was also the
first one with 8 bit bytes and the kind of byte addressing that is now
used everywhere, and the first popular machine with a large regular
set of registers.
The PDP-6 had something close to 16 registers in its lowest 16
words of memory, but I guess it is possible to argue that it
wasn't very popular (but the PDP-10 later was), and that these
memory locations were not really registers; if I read correctly,
it was possible to put code into them and run it.
(a fun alternative here was Intel's Larrabee/Xeon Phi, where they
raided their dusty chest of blueprints and produced a chip with
lots of tiny Pentium1 CPUs on it. There the architecture was fixed
into the programming model. It didn't do well, although not entirely
due to this choice)
Good points.
Definitely 16 registers, and yes, I would definitely call them
registers. The fact that they exist in memory space isn't that
important, nor that you could run code in them. They were treated
specially by the instructions.
And the PDP-6 was before the S/360. But it's also worth noting that the PDP-6 (and descendants) are a computer architecture that have now been
dead for over 30 years.
The PDP-11 (at least some models) have the exact same behavior with the registers. The CPU registers do exist in memory space, and you can run
code in them.
The main point on a PDP10 of putting code into the registers was that it went a lot faster - no memory access required.
On Mon, 4 Sep 2023 16:36:54 +0100
Vir Campestris <vir.campestris@invalid.invalid> wrote:
The main point on a PDP10 of putting code into the registers was that it
went a lot faster - no memory access required.
The TI 990/9900 series of machines had the general purpose registers
in memory pointed to by a CPU based register - context switching simply involved pointing at a different bit of memory to get a new set of
registers. It made for very fast context switching and slow register operations - an interesting trade off.
On 04/09/2023 14:43, Johnny Billquist wrote:
Good points.
Definitely 16 registers, and yes, I would definitely call them
registers. The fact that they exist in memory space isn't that
important, nor that you could run code in them. They were treated
specially by the instructions.
And the PDP-6 was before the S/360. But it's also worth noting that
the PDP-6 (and descendants) are a computer architecture that have now
been dead for over 30 years.
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can
run code in them.
I've always assumed that the registers were _saved_ into memory space
when the process was stopped.
The main point on a PDP10 of putting code into the registers was that it went a lot faster - no memory access required.
On 2023-09-04 17:36, Vir Campestris wrote:
On 04/09/2023 14:43, Johnny Billquist wrote:
Good points.
Definitely 16 registers, and yes, I would definitely call them
registers. The fact that they exist in memory space isn't that
important, nor that you could run code in them. They were treated
specially by the instructions.
And the PDP-6 was before the S/360. But it's also worth noting that
the PDP-6 (and descendants) are a computer architecture that have now
been dead for over 30 years.
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you
can run code in them.
I've always assumed that the registers were _saved_ into memory space
when the process was stopped.
The main point on a PDP10 of putting code into the registers was that
it went a lot faster - no memory access required.
As far as I know/can remember, there was the fast register option for
the KI10 (or was it KA?) which actually sat on top of the normal memory, meaning the first 16 words of main memory was never used. And instead
you had some really fast memory there.
But if you didn't have it, then normal memory was used. With the KL and
KS I wouldn't know for sure. There is no obvious easy way to tell, I
think. But for the machine that had the fastmem option, it was fairly obvious.
Ahem A Rivet's Shot <steveo@eircom.net> schrieb:
On Mon, 4 Sep 2023 16:36:54 +0100
Vir Campestris <vir.campestris@invalid.invalid> wrote:
The main point on a PDP10 of putting code into the registers was that
it went a lot faster - no memory access required.
The TI 990/9900 series of machines had the general purpose
registers in memory pointed to by a CPU based register - context
switching simply involved pointing at a different bit of memory to get
a new set of registers. It made for very fast context switching and
slow register operations - an interesting trade off.
Or subroutine calls...
In the age of the 6502, when memory ran twice as fast as the CPU, this
was feasible. Not so much nowadays, where you can wait 150 cycles for
a main memory access.
On 04/09/2023 14:43, Johnny Billquist wrote:
Good points.
Definitely 16 registers, and yes, I would definitely call them
registers. The fact that they exist in memory space isn't that
important, nor that you could run code in them. They were treated
specially by the instructions.
And the PDP-6 was before the S/360. But it's also worth noting that the
PDP-6 (and descendants) are a computer architecture that have now been
dead for over 30 years.
The PDP-11 (at least some models) have the exact same behavior with the
registers. The CPU registers do exist in memory space, and you can run
code in them.
I've always assumed that the registers were _saved_ into memory space
when the process was stopped.
The TI 990/9900 series of machines had the general purpose
registers in memory pointed to by a CPU based register -
context switching simply involved pointing at a different
bit of memory to get a new set of registers. It made for
very fast context switching and slow register operations
- an interesting trade off.
On 2023-09-04 13:02, Thomas Koenig wrote:
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can
run code in them.
Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
Johnny Billquist <bqt@softjar.se> writes:
On 2023-09-04 13:02, Thomas Koenig wrote:
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can
run code in them.
I don't remember ever coming across this -- which models?
I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its index registers in core (not backing real registers, although the 1800 did have real registers too).
Johnny Billquist <bqt@softjar.se> writes:
On 2023-09-04 13:02, Thomas Koenig wrote:
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can
run code in them.
I don't remember ever coming across this -- which models?
Peter Flass <peter_flass@yahoo.com> writes:
Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
Johnny Billquist <bqt@softjar.se> writes:
On 2023-09-04 13:02, Thomas Koenig wrote:
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can >>>> run code in them.
I don't remember ever coming across this -- which models?
I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its index
registers in core (not backing real registers, although the 1800 did have
real registers too).
Yes, there were several other computer families that did it. It's >specifically PDP 11 where I haven't heard of it before.
Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
Peter Flass <peter_flass@yahoo.com> writes:
Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
Johnny Billquist <bqt@softjar.se> writes:
On 2023-09-04 13:02, Thomas Koenig wrote:
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can >>>>> run code in them.
I don't remember ever coming across this -- which models?
I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its index
registers in core (not backing real registers, although the 1800 did have >>> real registers too).
Yes, there were several other computer families that did it. It's
specifically PDP 11 where I haven't heard of it before.
Indeed, the Burroughs BCD machines also had their index registers
in low memory.
Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
Peter Flass <peter_flass@yahoo.com> writes:
Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
Johnny Billquist <bqt@softjar.se> writes:I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its
On 2023-09-04 13:02, Thomas Koenig wrote:
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you
can run code in them.
I don't remember ever coming across this -- which models?
index registers in core (not backing real registers, although the 1800
did have real registers too).
Yes, there were several other computer families that did it. It's >>specifically PDP 11 where I haven't heard of it before.
Indeed, the Burroughs BCD machines also had their index registers in low memory.
On 2023-09-06 17:49, Joe Pfeiffer wrote:
Johnny Billquist <bqt@softjar.se> writes:
On 2023-09-04 13:02, Thomas Koenig wrote:I don't remember ever coming across this -- which models?
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can
run code in them.
I won't dare trying to list them all. I know that the 11/70 have it,
which implies that the 11/45, 11/50 and 11/55 also do. My guess is
that all PDP-11s, except those that have a serial console built into
the CPU. So anything except the F11 and J11 based. Possibly also T11.
General register set 0 is at 17777700 to 17777707. General register
set 1 is at 17777710 to 17777717. The weird/funny thing is that when
you access these addresses on the front panel, addresses actually
increment by 1, and not the usual 2. But they are still 16 bit data on
each address (obviously, since they are the CPU registers).
Quadibloc <jsavard@ecn.ab.ca> wrote:
On Thursday, August 31, 2023 at 4:37:55 AM UTC-6, Theo Markettos wrote: >>> Elijah Stone <elr...@elronnd.net> wrote:
I am looking for information on the history and development of ISAs as a >>>> technology. Including:
- Why were they invented? (IBM wanted to sell their customers hardware >>>> upgrades without requiring that they rewrite their code?)
I think this is slightly the wrong question. Every stored program computer >>> has an ISA, being the encoding of stored instructions to logical operations.
In the early days the ISA was unique to the machine, but the machines
started as one-offs anyway.
But given his reference to IBM, apparently he is thinking of the ISA as existing
as a "thing" only when it is shared by more than one model of a computer.
Since the EDSAC and the EDVAC, built separately according to the same plan, >> shared an instruction set, but were also basically the same implementation, I'm
not sure they would count by his standards.
Before the IBM 360, the IBM 709 was upwards-compatible with the IBM 704,
and Univac made the 1103 and the 1103A.
The SDS 910, 920, and 930 were a series of three machines of different sizes >> available from Scientific Data Systems which shared an instruction set for a >> 24-bit word. And the GE 225 and 235 were part of a compatible series with a >> 20 bit word also.
I wasn’t aware of the incompatibilities among various PDP-11 models, but >the -10s seemed to have areas of incompatibility also. I believe IBM was
the first to define an “architecture” independent of any particular >implementation, and then make sure (nearly) all S/360 models conformed to
it.
I wasn’t aware of the incompatibilities among various PDP-11 models, but the -10s seemed to have areas of incompatibility also. I believe IBM was
the first to define an “architecture” independent of any particular implementation, and then make sure (nearly) all S/360 models conformed to
it.
On 2023-09-06 17:49, Joe Pfeiffer wrote:
Johnny Billquist <bqt@softjar.se> writes:
On 2023-09-04 13:02, Thomas Koenig wrote:
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can
run code in them.
I don't remember ever coming across this -- which models?
I won't dare trying to list them all. I know that the 11/70 have it,
which implies that the 11/45, 11/50 and 11/55 also do.
General register set 0 is at 17777700 to 17777707. General register set
1 is at 17777710 to 17777717.
According to Johnny Billquist <bqt@softjar.se>:
On 2023-09-06 17:49, Joe Pfeiffer wrote:
Johnny Billquist <bqt@softjar.se> writes:
On 2023-09-04 13:02, Thomas Koenig wrote:
The PDP-11 (at least some models) have the exact same behavior with
the registers. The CPU registers do exist in memory space, and you can >>>> run code in them.
I don't remember ever coming across this -- which models?
I won't dare trying to list them all. I know that the 11/70 have it,
which implies that the 11/45, 11/50 and 11/55 also do.
I did a lot of programming on an an 11/45 and I can assure you the
registers were addressable as memory, at least not in any normal way.
General register set 0 is at 17777700 to 17777707. General register set
1 is at 17777710 to 17777717.
That was for debugging. It wasn't useful in normal code.
--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly
John Levine <johnl@taugh.com> schrieb:
The 360 was such a great success that we now often forget how
revolutionary it was. It was not only the first architecture intended
from the outset to have multiple implmementations, but it was also the
first one with 8 bit bytes and the kind of byte addressing that is now
used everywhere, and the first popular machine with a large regular
set of registers.
The PDP-6 had something close to 16 registers in its lowest 16
words of memory, but I guess it is possible to argue that it
wasn't very popular ...
I wasn't aware of the incompatibilities among various PDP-11 models, but the -10s seemed to have areas of incompatibility also. I believe IBM was the first to define an "architecture" independent of any particular implementation, and then make sure (nearly) all S/360 models conformed to it.
According to Thomas Koenig <tkoenig@netcologne.de>:
John Levine <johnl@taugh.com> schrieb:
The 360 was such a great success that we now often forget how revolutionary >>> it was. It was not only the first architecture intended from the outset to >>> have multiple implmementations, but it was also the first one with 8 bit >>> bytes and the kind of byte addressing that is now used everywhere, and the >>> first popular machine with a large regular set of registers.
The PDP-6 had something close to 16 registers in its lowest 16 words of
memory, but I guess it is possible to argue that it wasn't very popular ...
I actually programmed a PDP-6 when I was in high school.
The first 16 memory locations were the registers. On the PDP-6 and KA-10, transistor registers were optional, otherwise stored in the first 16 locations of core, but everyone bought the fast registers so they became standard on the KI-10.
The PDP-6 was a technical triumph but a commercial failure. They used large boards with unreliable connectors making the machine flaky. DEC only made 20 of them, and cancelled the product. It's not entirely clear to me why they gave the -10 another try but it was clearly a good move.
S/360 and the PDP-6 were both announced in 1964, so they obviously both had been designed some time before, as far as I know without either having knowledge of the other. The first 360s were shipped in 1965, so DEC probably shipped a PDP-6 before IBM shipped a 360, but I would say they were simultaneous, and the -6 definitely was not popular, even though it was well loved by its friends.
S/360 and the PDP-6 were both announced in 1964, so they obviously
both had been designed some time before, as far as I know without
either having knowledge of the other. The first 360s were shipped in
1965, so DEC probably shipped a PDP-6 before IBM shipped a 360, but I
would say they were simultaneous, and the -6 definitely was not
popular, even though it was well loved by its friends.
The PDP-10 was designed using the new technology introduced with the PDP-7, the
FlipChip(TM), and used to good effect in the PDP-8 and PDP-9. The 36 bit >architecture redesign was a skunkworks project, hidden from Ken Olsen until it >was ready to go; the initial product line included three models (the 10/10, >10/20, and 10/30) which were nominally single user systems, to make KO happy, >as well as a nonswapping (10/40) and a swapping (10/50) multiuser model.
It is reported that someone did order a 10/30.[1]
The System/360 family were announced in April, 1964, with first customer ship >in October, 1965.
The PDP-6 was announced three weeks before, in March, 1964, with first customer
ship in June, 1964.
A lot less vapor in the PDP-6 than in the S/360, don't you think?
Johnny Billquist wrote:
On 2023-09-10 00:24, Rich Alderson wrote:
Other than the addition of extended addressing to the KL-10 and KS-10, what >>> did you have in mind for the PDP-10 systems? Asking for a friend... ;->Was byte instructions always in there?
Or was that something that changed just between the -6 and -10?
Yes, they were theresince the PDP-6. On the KA10 they were "optional".
There were some minor changes between the PDP-6 and the KA10. They are easily avoidable, but strictly speaking, they were not 100% compatible. The KI10 added a few instructions, but was otherwise backwards compatible. The KL10 added a bunch of new instructions. The KS10 kept the same user mode instruction set.
Johnny Billquist wrote:
So there are some incompatibilities between PDP-10 models. Not as many
as for the PDP-11, and it's more in the line of added instructions. But
it still means differences exist. Which a program could even use to
figure out what model of CPU it is running on.
Yes, and there even were such programs in the official DEC documentations. However, they don't use any instructions are are undefined on the earlier models, but more minute details.
If you’re not 100% compatible, it’s going to come back and bite someone.
Johnny Billquist <bqt@softjar.se> wrote:
On 2023-09-10 18:11, Lars Brinkhoff wrote:
Johnny Billquist wrote:
So there are some incompatibilities between PDP-10 models. Not as many >>>> as for the PDP-11, and it's more in the line of added instructions. But >>>> it still means differences exist. Which a program could even use to
figure out what model of CPU it is running on.
Yes, and there even were such programs in the official DEC
documentations. However, they don't use any instructions are are
undefined on the earlier models, but more minute details.
Oh ho... More differences then. :-)
Like on a PDP-11, where SWAB might set or clear the V flag, depending on
model.
Or how a PDP-8 reacts if you combine RAL and RAR.
So much fun with the weird small details.
If you’re not 100% compatible, it’s going to come back and bite someone.
Peter Flass <peter_flass@yahoo.com> writes:
I wasn't aware of the incompatibilities among various PDP-11 models, but the >> -10s seemed to have areas of incompatibility also. I believe IBM was the
first to define an "architecture" independent of any particular
implementation, and then make sure (nearly) all S/360 models conformed to
it.
Other than the addition of extended addressing to the KL-10 and KS-10, what did you have in mind for the PDP-10 systems? Asking for a friend... ;->
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